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Wafer Level Packaging

Today’s consumers are looking for powerful, multi-functional electronic devices with unprecedented performance and speed, yet small, thin, and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. 

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Technical Highlights
Wafer Level Packaging
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High-performance fan-out WLP (eWLB & ECP) with outstanding bandwidth, performance, size, and cost advantages
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The eWLB platform enables smaller footprints and higher I/O density for more efficient package designs
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Millimeter-wave-optimized wafer-level AiP antenna solutions offering improved high-frequency performance, shorter interconnects, lower conductor loss, and optimized dielectric properties
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2D/2.5D/3D WLP integration—side-by-side or stacked chips, embedded devices, dual-sided RDL—to enable complex PoP and SiP solutions.
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Five-sided protection via FI-ECP and eWLCSP wafer-level technologies
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BGBM packaging—wafer-thinning plus backside metallization—for enhanced thermal diffusion, electrical performance, and reduced impedance, ideal for MOSFETs, IGBTs, and other vertical-structure devices
Applications
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5G Mobile Processors
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Wi-Fi Routers & Power Amplifiers
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Wearable Devices
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AI & Enterprise Servers
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Communication Infrastructure
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Processors
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